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| HM514100C Series 4,194,304-word x 1-bit Dynamic Random Access Memory Description The Hitachi HM514100C is a CMOS dynamic RAM organized 4,194,304 word x 1-bit. HM514100C has realized higher density, higher performance and various functions by employing 0.8 m CMOS process technology and some new CMOS circuit design technologies. The HM514100C offers Fast Page Mode as a high speed access mode. Multiplexed address input permits the HM514100C to be packaged in standard 300-mil 26-pin plastic SOJ, standard 400-mil 20-pin plastic ZIP and 26-pin plastic TSOP II. Features * Single 5 V (10%) * High speed Access time : 60 ns/70 ns/80 ns (max) * Low power dissipation Active mode : 605 mW/550 mW/495 mW (max) Standby mode : 11 mW (max) 0.55 mW (max) (L-version) * Fast page mode capability * 1024 refresh cycles : 16 ms : 128 ms (L-version) * 3 variations of refresh RAS-only refresh CAS-before-RAS refresh Hidden refresh * Test function * Battery backup operation (L-version) HM514100C Series Ordering Information Type No. HM514100CS-6 HM514100CS-7 HM514100CS-8 HM514100CLS-6 HM514100CLS-7 HM514100CLS-8 HM514100CZ-6 HM514100CZ-7 HM514100CZ-8 HM514100CLZ-6 HM514100CLZ-7 HM514100CLZ-8 HM514100CTT-6 HM514100CTT-7 HM514100CTT-8 HM514100CLTT-6 HM514100CLTT-7 HM514100CLTT-8 Access Time 60 ns 70 ns 80 ns 60 ns 70 ns 80 ns 60 ns 70 ns 80 ns 60 ns 70 ns 80 ns 60 ns 70 ns 80 ns 60 ns 70 ns 80 ns 26-pin plastic TSOPII (TTP-26/20D) 400-mil 20-pin plastic ZIP (ZP-20) Package 300-mil 26-pin plastic SOJ (CP-26/20D) 2 HM514100C Series Pin Arrangement HM514100CS/CLS Series HM514100CZ/CLZ Series Din WE RAS NC A10 1 2 3 4 5 26 25 24 23 22 VSS Dout CAS 1 A9 CAS 2 3 Dout VSS 4 5 Din WE 6 7 RAS A10 8 9 NC NC 10 11 A0 A1 12 13 A2 A3 14 15 VCC A4 16 17 A5 A6 18 19 A7 A8 20 NC A9 A0 A1 A2 A3 VCC 9 10 11 12 13 18 17 16 15 14 A8 A7 A6 A5 A4 (Top view) (Bottom view) HM514100CTT/CLTT Series Din WE RAS NC A10 1 2 3 4 5 26 25 24 23 22 VSS Dout CAS NC A9 A0 A1 A2 A3 VCC 9 10 11 12 13 18 17 16 15 14 A8 A7 A6 A5 A4 (Top view) 3 HM514100C Series Pin Description Pin Name A0 to A10 A0 to A9 Din Dout RAS CAS WE VCC VSS NC Function Address input Refresh address input Data-in Data-out Row address strobe Column address strobe Read/Write enable Power (+5 V) Ground No connection 4 Block Diagram Row Driver Row Driver RAS RAS Control Circuit 256 k Memory Array Mat I/O Bus & Column Decoder Row Driver Row Driver 256 k Memory Array Mat I/O Bus & Column Decoder 256 k Memory Array Mat 256 k Memory Array Mat I/O Bus & Column Decoder Row Driver 256 k Memory Array Mat Row Driver Row Driver CAS CAS Control Circuit 256 k Memory Array Mat Row Address Buffer Row Driver I/O Bus & Column Decoder 256 k Memory Array Mat 256 k Memory Array Mat WE WE Control Circuit Row Decoder & Peripheral Circuit Address A0-A10 Row Driver Row Driver Row Driver Row Driver Row Driver Row Driver Row Driver Row Driver 256 k Memory Array Mat 256 k Memory Array Mat I/O Bus & Column Decoder 256 k Memory Array Mat I/O Bus & Column Decoder 256 k Memory Array Mat Din 256 k Memory Array Mat 256 k Memory Array Mat I/O Bus & Column Decoder 256 k Memory Array Mat Column Address Buffer I/O Buffer I/O Bus & Column Decoder HM514100C Series Dout 256 k Memory Array Mat 5 HM514100C Series Absolute Maximum Ratings Parameter Voltage on any pin relative to V SS Supply voltage relative to VSS Short circuit output current Power dissipation Operating temperature Storage temperature Symbol VT VCC Iout PT Topr Tstg Value -1.0 to +7.0 -1.0 to +7.0 50 1.0 0 to +70 -55 to +125 Unit V V mA W C C Recommended DC Operating Conditions (Ta = 0 to +70C) Parameter Supply voltage Symbol VSS VCC Input high voltage Input low voltage Note: VIH VIL Min 0 4.5 2.4 -1.0 Typ 0 5.0 -- -- Max 0 5.5 6.5 0.8 Unit V V V V 1 1 1 Note 1. All voltage referred to VSS . 6 HM514100C Series DC Characteristics (Ta = 0 to +70C, VCC = 5 V 10%, VSS = 0 V) HM514100C -6 Parameter Operating current Standby current -7 -8 Notes 1, 2 Symbol Min Max Min Max Min Max Unit Test Conditions I CC1 I CC2 -- -- 110 -- 2 -- 100 -- 2 -- 90 2 mA mA RAS, CAS cycling t RC = min TTL interface RAS, CAS = VIH Dout = High-Z CMOS interface RAS, CAS V CC - 0.2 V Dout = High-Z CMOS interface RAS, CAS = VIH WE, Address and Din = VIH or VIL Dout = High-Z t RC = min RAS = VIH, CAS = VIL Dout = enable t RC = min t PC = min t RC = 125 s t RAS 1 s WE = VIH, CAS = VIL OE Address, Din = VIH or VIL Dout = High-Z 0 V Vin 7 V 0 V Vout 7 V Dout = disable High Iout = -5 mA Low Iout = 4.2 mA -- 1 -- 1 -- 1 mA Standby current (L-version) I CC2 -- 100 -- 100 -- 100 A 4 RAS-only refreshcurrent Standby current I CC3 I CC5 -- -- 110 -- 5 -- 100 -- 5 -- 90 5 mA mA 2 1 CAS-before-RAS refresh current Fast page mode current Battery backup current (Standby with CBR refresh) (L-version) I CC6 I CC7 I CC10 -- -- -- 110 -- 110 -- 200 -- 100 -- 100 -- 200 -- 90 90 200 mA mA A 1, 3 4 Input leakage current Output leakage current I LI I LO -10 10 -10 10 2.4 0 VCC 0.4 -10 10 -10 10 2.4 0 VCC 0.4 -10 10 -10 10 2.4 0 VCC 0.4 A A V V Output high voltage VOH Output low voltage VOL Notes: 1. I CC depends on output load condition when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed twice or less while RAS = VIL. 3. Address can be changed once or less while CAS = VIH. 4. VCC - 0.2 V V IH 6.5 V and 0 V V IL 0.2 V. 7 HM514100C Series Capacitance (Ta = 25C, VCC = 5 V 10%) Parameter Input capacitance (Address, Data-in) Input capacitance (Clocks) Output capacitance (Data-out) Symbol CI1 CI2 CO Typ -- -- -- Max 5 7 7 Unit pF pF pF Notes 1 1 1, 2 Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIH to disable Dout. AC Characteristics (Ta = 0 to +70C, VCC = 5 V 10%, VSS = 0 V)*1, *12, *15 Test Conditions * Input rise and fall time : 5 ns * Input timing reference levels : 0.8 V, 2.4 V * Output load : 2 TTL gate + C L (100 pF) (Including scope and jig) Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters) HM514100C -6 Parameter Random read or write cycle time RAS precharge time RAS pulse width CAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS to column address delay time RAS hold time CAS hold time CAS to RAS precharge time Transition time (rise and fall) Refresh period Refresh period (L-version) Symbol Min Max t RC t RP t RAS t CAS t ASR t RAH t ASC t CAH t RCD t RAD t RSH t CSH t CRP tT t REF t REF 110 -- 40 60 15 0 10 0 15 20 15 15 60 10 3 -- -- -- 10000 10000 -- -- -- -- 45 30 -- -- -- 50 16 128 -7 Min Max 130 -- 50 70 20 0 10 0 15 20 15 20 70 10 3 -- -- -- 10000 10000 -- -- -- -- 50 35 -- -- -- 50 16 128 -8 Min Max 150 -- 60 80 20 0 10 0 15 20 15 20 80 10 3 -- -- -- 10000 10000 -- -- -- -- 60 40 -- -- -- 50 16 128 Unit Notes ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms 7 8 9 18 19 8 HM514100C Series Read Cycle HM514100C -6 Parameter Access time from RAS Access time from CAS Access time from address Read command setup time Read command hold time to CAS Read command hold time to RAS Column address to RAS lead time Output buffer turn-off time Symbol Min Max t RAC t CAC t AA t RCS t RCH t RRH t RAL t OFF -- -- -- 0 0 0 30 0 60 15 30 -- -- -- -- 15 -7 Min Max -- -- -- 0 0 0 35 0 70 20 35 -- -- -- -- 20 -8 Min -- -- -- 0 0 0 40 0 Max 80 20 40 -- -- -- -- 20 Unit Notes ns ns ns ns ns ns ns ns 6 17 17 2, 3, 16 3, 4, 14, 16 3, 5, 14, 16 Write Cycle HM514100C -6 Parameter Write command setup time Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Data-in setup time Data-in hold time Symbol Min Max t WCS t WCH t WP t RWL t CWL t DS t DH 0 15 10 15 15 0 15 -- -- -- -- -- -- -- -7 Min Max 0 15 10 20 20 0 15 -- -- -- -- -- -- -- -8 Min Max 0 15 10 20 20 0 15 -- -- -- -- -- -- -- Unit Notes ns ns ns ns ns ns ns 11 11 10 Read-Modify-Write Cycle HM514100C -6 Parameter Read-modify-write cycle time RAS to WE delay time CAS to WE delay time Column address to WE delay time Symbol Min Max t RWC t RWD t CWD t AWD 130 -- 60 15 30 -- -- -- -7 Min Max 155 -- 70 20 35 -- -- -- -8 Min Max 175 -- 80 20 40 -- -- -- Unit Notes ns ns ns ns 10 10 10 9 HM514100C Series Refresh Cycle HM514100C -6 Parameter Symbol Min Max 10 10 10 10 -- -- -- -- -7 Min Max 10 10 10 10 -- -- -- -- -8 Min Max 10 10 10 10 -- -- -- -- Unit Notes ns ns ns ns CAS setup time (CBR refresh cycle) t CSR CAS hold time (CBR refresh cycle) RAS precharge to CAS hold time t CHR t RPC CAS precharge time in normal mode t CPN Fast Page Mode Cycle HM514100C -6 Parameter Fast page mode cycle time Symbol Min Max t PC 40 10 -- -- 35 -- -- -7 Min Max 45 10 -- -- -8 Min Max 50 10 -- -- Unit Notes ns ns 13 3, 14, 16 Fast page mode CAS precharge time t CP Fast page mode RAS pulse width Access time from CAS precharge RAS hold time from CAS precharge t RASC t ACP t RHCP 100000 -- 35 -- -- 40 100000 -- 40 -- -- 45 100000 ns 45 -- ns ns Fast Page Mode Read-Modify-Write Cycle HM514100C -6 Parameter Fast page mode read-modify-write cycle time CAS precharge to WE delay time Symbol Min Max t PCM t CPW 60 35 -- -- -7 Min Max 70 40 -- -- -8 Min Max 75 45 -- -- Unit Notes ns ns 10 Test Mode Cycle HM514100C -6 Parameter Test mode WE setup time Test mode WE hold time Symbol Min Max t WS t WH 0 10 -- -- -7 Min Max 0 10 -- -- -8 Min Max 0 10 -- -- Unit Notes ns ns 10 HM514100C Series Counter Test Cycle HM514100C -6 Parameter CAS precharge time in counter test cycle Symbol Min Max t CPT 40 -- -7 Min Max 40 -- -8 Min Max 40 -- Unit Notes ns Notes: 1. AC measurements assume t T = 5 ns. 2. Assumes that t RCD tRCD (max) and tRAD tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 3. Measured with a load circuit equivalent to 2 TTL loads and 100 pF. 4. Assumes that t RCD tRCD (max) and tRAD tRAD (max). 5. Assumes that t RCD tRCD (max) and tRAD tRAD (max). 6. t OFF (max) defines the time at which the output achieves the open circuit condition and is not referred to output voltage levels. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between V IH and VIL. 8. Operation with the t RCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only, if t RCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC . 9. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only, if t RAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA . 10. t WCS , t RWD, t CWD, t AWD and tCPW are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only; if t WCS tWCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if t RWD tRWD (min), tCWD tCWD (min), tAWD tAWD (min) and tCPW tCPW (min) , the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 11. These parameters are referred to CAS leading edge in an early write cycle and to WE leading edge in a delayed write or read-modify-write cycle. 12. An initial pause of 100 s is required after power up followed by a minimum of eight initializa-tion cycles (RAS-only refresh cycle or CAS-before-RAS refresh cycle). If the internal refresh counter is used, a minimum of eight CAS-before-RAS refresh cycles is required. 13. t RASC defines RAS pulse width in fast page mode cycles. 14. Access time is determined by the longer of t AA or tCAC or tACP. 15. Test mode operation specified in this data sheet is 8-bit test function controlled by control address bits - - - RA10, CA10 and CA0. This test mode operation can be performed by WE-and-CASbefore-RAS (WCBR) refresh cycle. Refresh during test mode operation will be performed by normal read cycles or by WCBR refresh cycles. When the state of eight test bits accord each other, the condition of the output data is high level. When the state of test bits do not accord, the condition of the output data is low level. Data output pin is Dout and data input pin is Din. In order to end this test mode operation, perform a CAS-before-RAS refresh cycle or a RAS-only refresh cycle. 16. In a test mode read cycle, the value of tRAC , t AA , t CAC and t ACP is delayed for 2 ns to 5 ns for the specified value. These parameters should be specified in test mode cycles by adding the above value to the specified value in this data sheet. 17. Either t RCH or tRRH must be satisfied 11 HM514100C Series 18. t RAS (min) = tRWD (min) + tRWL (min) + tT in read-modify-write cycle. 19. t CAS (min) = tCWD (min) + tCWL (min) + tT in read-modify-write cycle. 20. XXX: H or L (H: V IH (min) V IN V IH (max), L: VIL (min) V IN V IL (max)) ///////: Invalid Dout Timing Waveforms*20 Read Cycle t RC t RAS t RP RAS t CSH t RCD tT t RSH t CAS t CRP CAS t RAD t ASR t RAH t ASC t RAL t CAH Address Row Column t RRH t RCS t RCH WE t CAC t AA t RAC t OFF Dout Dout 12 HM514100C Series Early Write Cycle t RC t RAS t RP RAS t CSH t RCD tT t RSH t CAS t CRP CAS t ASR tRAH t ASC t CAH Address Row Column t WCS t WCH WE t DS t DH Din Din Dout High-Z * t WCS t WCS (min) 13 HM514100C Series Delayed Write Cycle t RC t RAS t RP RAS t CSH t RCD tT t RSH t CAS t CRP CAS t CAH t ASR t RAH t ASC Address Row Column t CWL t RWL t RCS t WP WE t DH t DS * Din Din t OFF Dout Invalid Dout 14 HM514100C Series Read-Modify-Write Cycle t RWC t RAS t RP RAS tT t RCD t CAS t CRP CAS t RAD t ASR t RAH t ASC t CAH Address Row t RCS Column t CWD t AWD t RWD t CWL t RWL t WP WE t DS t DH Din t CAC t RAC t AA Din t OFF Dout Dout 15 HM514100C Series Hidden Refresh Cycle t RC t RAS (Read) RAS tT t RSH t RCD t CAS t CHR t CRP t RP t RC t RAS (Refresh) t RC t RP t RAS (Refresh) t RP CAS t RAD t ASR Address t RAH t ASC t RAL t CAH Column t RCH t RCS t RRH Row WE t CAC t AA t RAC t OFF Dout Dout 16 HM514100C Series Fast Page Mode Read Cycle t RASC t RHCP RAS t RP tT t CSH t RCD CAS t CAS t CP t PC t CAS t CP t RSH t CAS tCRP t RAD t ASR t RAH t ASC t CAH t ASC t CAH t ASC t RAL t CAH Address Row Column Column t RCS Column t RCS tRRH t RCH t RCS t RCH t RCH WE t CAC t AA t RAC t OFF t AA t ACP t OFF t CAC t CAC t AA tACP t OFF Dout Dout Dout Dout 17 HM514100C Series Fast Page Mode Early Write Cycle t RASC t RP RAS tT t CSH t RCD t CAS t CP t PC t CAS t CP t RSH t CAS t CRP CAS t ASR t RAH t ASC t CAH t ASC t CAH t ASC t CAH Address Row Column Column Column t WCS t WCH t WCS t WCH t WCS t WCH WE t DS t DH t DS t DH t DS t DH Din Din Din Din Dout High-Z * t WCS t WCS (min) 18 HM514100C Series Fast Page Mode Delayed Write Cycle t RASC t RSH RAS tT t CSH t RCD t CAS t PC t CP t CAS t CP t RWL t CAS t CRP t RP CAS t ASR t RAH t ASC t CAH Column t CWL t RCS t WP WE t DH t DS t RCS t DS t DH t RCS t DS Din t DH t ASC t CAH t ASC t CAH Address Row Column t CWL t WP Column t CWL t WP + * $ t OFF t OFF t OFF Dout Invalid Dout Invalid Dout Invalid Dout Din Din Din 19 HM514100C Series Fast Page Mode Read-Modify-Write Cycle t RASC t RP RAS tT t RCD tCAS t CP t PCM t CAS t CP t RWL t CAS t CRP CAS tCAH t CAH Column t RCS t ASC t ASC t CWL t CAH t ASR t ASC tRAH Address Row Column t CWD Column t CWL t RAD t RWD WE t AWD t RCS t CWD t DS t DH Din Din t CAC t AA t RAC t OFF t ACP t AA Dout Dout 20 , t AWD t WP t CWD t WP t WP t RCS t CPW tCPW t DS t DS t DH t DH Din t CAC t ACP t AA t OFF t OFF Din t CAC Dout Dout t CWL t AWD HM514100C Series Test Mode Cycle *,** Reset Cycle Set Cycle** Test Mode Cycle Normal Mode RAS CAS WE * CBR or RAS-only refresh ** Address, Din: H or L 21 HM514100C Series Test Mode Set Cycle WE-and-CAS-Before RAS-Refresh t RC t RP t RAS t RP RAS t RPC t CSR tT CAS t CPN t WS t CHR t RPC t CRP t WH WE Address t OFF Dout High-Z SC QB C@ A , S R P t CPN * Din : H or L 22 HM514100C Series CAS-Before-RAS Refresh Cycle t RC t RP t RAS t RP RAS tT t CPN t RPC t CSR t CHR t CPN t RPC t CRP , t WS t WH WE Address t OFF Dout High-Z CAS * Din : H or L 23 HM514100C Series RAS-Only Refresh Cycle t RC t RAS t RP RAS tT t CRP tRPC tCRP CAS t ASR t RAH Address Row Dout High-Z * Refresh address : A0 - A9 (AX0 - AX9) ** Din, WE : H or L 24 HM514100C Series CAS-Before-RAS Refresh Counter Check Cycle (Read) t RP RAS tT t CSR t CHR t CPT t RSH t CAS tCRP CAS t ASC t CAH Address Column t RCH t RRH t WS t WH t RCS WE t AA t CAC t OFF Dout Dout 25 HM514100C Series CAS-Before-RAS Refresh Counter Check Cycle (Write) t RAS RAS tT t CSR t CHR t CPT t RSH t CAS t CRP t RP CAS t ASC t CAH Address Column t WS t WH t WCS t WCH WE t DS t DH Din Din Dout High-Z 26 HM514100C Series Package Dimensions HM514100CS/CLS Series (CP-26/20D) 16.90 17.27 Max 22 18 Unit: mm 26 14 7.62 0.13 1 3.50 0.26 5 0.74 1.30 Max 9 13 0.21 2.40 + 0.24 - 8.51 0.13 0.80 6.71 0.28 +0.25 -0.17 0.43 0.10 0.10 1.27 HM514100CZ/CLZ Series (ZP-20) Unit: mm 25.61 26.11 Max 2.80 Min 10.16 Max 8.51 0.25 - 0.05 + 0.10 1 0.50 - 0.12 + 0.08 20 1.27 0.3 M 1.14 Max 2.85 2.54 27 HM514100C Series HM514100CTT/CLTT Series (TTP-26/20D) 17.14 17.54 Max 26 22 18 14 7.62 Unit: mm 1 5 1.27 9 13 0.40 0.10 0.21 1.15 Max M 9.22 0.2 0 - 5 0.13 0.05 1.20 Max 0.10 0.17 0.05 5.08 0.80 0.50 0.10 28 |
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